Starred repositories
Генерация SystemVerilog кода и документации для регистровой карты из IP-XACT XML описания
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
The Free and Open Source Cross Platform YUV Viewer with an advanced analytics toolset
Alliance for Open Media Video Codec reference implementation (Mozilla branch)
a tool for backing up your data using rsync (if you want to get help, use https://lists.sourceforge.net/lists/listinfo/rsnapshot-discuss)
Functional Coverage for SystemC (FC4SC) library which provides mechanisms for functional coverage definition, collection and reporting.
Python packages providing a library for Verification Stimulus and Coverage
Unified Coverage Interoperability Standard (UCIS)
Python API to Unified Coverage Interoperability Standard (UCIS) Data
Threejs/glm (C++)/pyglet/Unity examples for deep understanding of projection matrix (OpenGL)
✨ Light and Fast AI Assistant. Support: Web | iOS | MacOS | Android | Linux | Windows
Python-based Hardware Design Processing Toolkit for Verilog HDL
Syntax highlighting for Synopsys Register Abstraction Layer ralf files
svlib from http://www.verilab.com/resources/svlib/
Python module to extract comments from source code files of various types.
This unofficial extension integrates Draw.io (also known as diagrams.net) into VS Code.
Verilator open-source SystemVerilog simulator and lint system