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sv_docs Public
A UVM-style SystemVerilog HTML document generator, updated from the accellera git repo.
Perl GNU General Public License v3.0 UpdatedSep 7, 2025 -
sv_shortreal_to_fp16 Public
Transform SystemVerilog shortreal(float) type to FP16 bit vector according to IEEE 754, for AI chip verification etc.
SystemVerilog MIT License UpdatedAug 14, 2025 -
yuu_register_productor Public
UVM register utility generation by inputting xls table
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ac_types Public
Forked from hlslibs/ac_typesAlgorithmic C Datatypes
C++ Apache License 2.0 UpdatedAug 7, 2023 -
yuu_uvm_tb_gen_lite Public
Lightweight common UVM TB generator
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yuu_clock Public
UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
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yuu_vip_gen Public
UVM VIP architecture generator
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yuu_apb Public
UVM APB VIP, part of AMBA3&AMBA4 feature supported
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You-need-to-know-css Public
Forked from l-hammer/You-need-to-know-css💄CSS tricks for web developers~
CSS Other UpdatedJul 6, 2020
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