I am an Electronics and Communication Engineering undergraduate from Aditya College of Engineering, passionate about VLSI Design and Functional Verification.
I work extensively with Verilog, SystemVerilog, and UVM using tools like Cadence, QuestaSim, and Vivado.

• RISC-V Processor Design & Verification – Custom 5-stage pipeline processor in Verilog.
• UART Protocol Design & Verification – Complete UART TX/RX with configurable baud rate.
• Floating Point Adder (FPU) – IEEE 754 Single Precision Adder.

• HDLs & Languages: Verilog, SystemVerilog, VHDL, C, Python
• Verification: UVM, Assertions, Testbench creation
• EDA Tools: Cadence Xcelium, QuestaSim, Vivado, EDA Playground
• Scripting: Python, Shell, TCL
• Protocols: AMBA (AXI, AHB), UART, I2C, SPI
• Others: Git, Linux, Waveform Debugging

• Cadence: Semiconductor 101, Digital IC Fundamentals, SystemVerilog Fundamentals
• NPTEL: Digital Design with Verilog (73%)
• Cisco: Programming Essentials in C
• Pearson: HTML & CSS

• 700+ GitHub contributions in the last year
• 1+ Verilog problems solved on HDLBits
• Daily practice of RTL design as part of #100DaysOfVerilog
• SystemVerilog learner focusing on functional verification