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中国大学MOOC查询测验/作业/考试答案,插件支持,测验支持选择/判断/填空。

Vue 400 26 Updated Jun 22, 2025

Verilog module for calculation of FFT.

Verilog 187 53 Updated Aug 22, 2012

Realtime Audio Processing on Artix-7 FPGA written in VHDL

VHDL 5 1 Updated Nov 18, 2022

FPGA based PCM oversampling FIR filter.

Verilog 11 1 Updated Aug 30, 2025

FPGA based, Real-time processing of audio, including voiceprint recognition, adaptive noise suppression, et al.

Verilog 14 Updated May 8, 2025

Sampling and processing of audio data from microphone arrays

VHDL 8 1 Updated Jul 6, 2025

Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA development board. Reads audio data from an external mic and …

Verilog 18 Updated Jul 10, 2020

Various HDL (Verilog) IP Cores

Verilog 841 226 Updated Jul 1, 2021

Student project for using audio on the DE2-115 FPGA development board.

Verilog 27 6 Updated Apr 28, 2018

Our project aimed at developing a Real-Time Speech Recognition Engine on an FPGA using Altera DE2 board. The system was designed so as to recognize the word being spoken into the microphone. As lar…

Verilog 6 Updated Jun 29, 2022

a project of voice processing on ACG525

2 Updated Nov 14, 2024

第八届集创赛紫光同创杯国二FPGA部分

Verilog 31 1 Updated Sep 23, 2024

第八届集创赛紫光同创杯音频处理国家二等奖

Python 24 1 Updated Oct 15, 2024

ROS 机器人系统课程设计(自主导航+YOLO目标检测+语音播报)

Makefile 56 8 Updated Mar 26, 2025

Python 27 8 Updated Nov 4, 2022

Tutorials about using the ROS Navigation stack.

C++ 301 110 Updated Mar 15, 2021

NUS ME5413 Autonomous Mobile Robotics Final Project

C++ 59 13 Updated Apr 29, 2024

A shared repository between Software, Embedded and FPGA teams to handle sending and receiving ultrasonic waves from the appropriate transducers. The project is based on Xilinix Zynq7000 board.

SystemVerilog 1 Updated Jan 14, 2025

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

Verilog 3 Updated Apr 27, 2016

This repository contains codes and texts related with the FPGA RTL Implementation of the Delay and Sum Beamformer

Verilog 20 5 Updated Apr 4, 2022

Open source ultrasound processing modules and building blocks

Jupyter Notebook 389 112 Updated May 23, 2025

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

Verilog 76 21 Updated Apr 27, 2016

课设项目,基于stm32,时间片论结构,驱动OLED显示温度历史曲线,具备(ESP8266-01S)物联网功能发送数据至手机APP,可PI计算输出控制温度方案,温度上下限声光报警

C 81 15 Updated Sep 7, 2020

Simplest ultrasonic ANTISPY voice recording jammer based on ATTINY13 / ATTINY85/45/25 / ARDUINO with PAM8403 / TPA3116D2 module driving piezo ultrasonic transducers (and optionally AD8933 signal ge…

C++ 295 60 Updated Nov 11, 2025

Verilog PCI express components

Verilog 1,455 373 Updated Apr 26, 2024

The idea is to do DSP on a FPGA with audio from microphones.

KiCad Layout 7 1 Updated Jul 4, 2016

Design and Implementation of Microphone Array using Spartan6 ic, cs5340 ic, and I2S protocol for recording the sound of the heart and lung

C 10 3 Updated Apr 10, 2024

Hardware Design Files for the Zynq PL. Mostly Verilog, some pieces like the patched ADI reference design VHDL.

VHDL 5 1 Updated Oct 9, 2017

Verilog implementation of a ultrasonic radar

Verilog 19 2 Updated Jan 7, 2018
Python 18 2 Updated May 15, 2024
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