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OpenDT Public
Simple FSAE Electric Drivetrain Design Tool
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sscs-ose-code-a-chip.github.io Public
Forked from sscs-ose/sscs-ose-code-a-chip.github.ioIEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
Jupyter Notebook Apache License 2.0 UpdatedApr 23, 2025 -
verible-linter-action Public
Forked from chipsalliance/verible-linter-actionAutomatic SystemVerilog linting in github actions with the help of Verible
Python Apache License 2.0 UpdatedOct 22, 2024 -
ASCON_code-a-chip Public
ASCON implementation for IEEE SSCS Code a Chip
Jupyter Notebook GNU General Public License v3.0 UpdatedNov 26, 2023 -
ECE6254_final_project Public
Implementation and evaluation of https://github.com/google/scaaml for Georgia Tech ECE 6254
Jupyter Notebook UpdatedApr 17, 2023 -
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bfv-python Public
Forked from acmert/bfv-pythonSimple Python implementation of BFV Homomorphic Encryption Scheme
Python UpdatedNov 17, 2022 -
caravel_user_project Public
Forked from efabless/caravel_user_projecthttps://caravel-user-project.readthedocs.io
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continue_with_sv Public
Software and resources to help Purdue students (and others) continue developing with SystemVerilog after losing access to proprietary tools.
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OpenLane Public
Forked from The-OpenROAD-Project/OpenLaneNOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Mag…
Verilog Apache License 2.0 UpdatedJun 12, 2021
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