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UC San Diego
- https://turakhia.ucsd.edu/
- @yatishturakhia
Stars
Easily build an UShER tree of genomes for any virus in RefSeq/GenBank
Wastewater-Based Epidemiology using Phylogenetic Placements
High throughput tool for tall and wide multiple sequence alignment.
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
Tool for fully-automated inference of species trees from raw genome assemblies
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RTL implementation of Flex-DPE.