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the UPWM pulses for left and right are misaligned for the standard-fidelity sigma delta.

Status: Open.

#21 In xmos/lib_sw_dac;

· henkmuller opened on Nov 4, 2025

Documentation could do with some diagrams to illustrate operation and architecture

Status: Open.

#15 In xmos/lib_sw_dac;

· ed-xmos opened on Sep 16, 2025

PWM stage outputs resID on port at first output

Status: Open.

#13 In xmos/lib_sw_dac;

· ed-xmos opened on Sep 16, 2025

Output goes full scale if not continuously fed with samples

Status: Open.

#12 In xmos/lib_sw_dac;

· ed-xmos opened on Sep 16, 2025

192kHz HP does not meet timing for 75MHz thread speed

Status: Open.

#24 In xmos/lib_sw_dac;

· ed-xmos opened on Sep 1, 2025

Add dithering before the quantiser

Status: Open.

#25 In xmos/lib_sw_dac;

· henkmuller opened on Apr 23, 2025

Negate signal by negating PWM signal

Status: Open.

#26 In xmos/lib_sw_dac;

· henkmuller opened on Apr 22, 2025

Clear modulator on stop stream

Status: Open.

#27 In xmos/lib_sw_dac;

· henkmuller opened on Mar 21, 2025