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AXI, AXI stream, Ethernet, and PCIe components in System Verilog
Companion software for Introduction to Radar Using Python and MATLAB
Custom-made draw.io-shapes - in the form of an importable library - for drawing circuits and conceptual drawings in draw.io.
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
Open source FPGA-based NIC and platform for in-network compute
krakenrf / kfr
Forked from kfrlib/kfrFast, modern C++ DSP framework, FFT, Sample Rate Conversion, FIR/IIR/Biquad Filters (SSE, AVX, AVX-512, ARM NEON)
Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"
My take on the Eudyptula kernel programming Challenge, with subjects, walkthrough & tests. The Eudyptula Challenge was a series of programming exercises for the Linux kernel, that started from a ve…
A battery included Flatpak package for the GNURadio Companion
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
Project F brings FPGAs to life with exciting open-source designs you can build on.
Collection of various algorithms in mathematics, machine learning, computer science, physics, etc implemented in C for educational purposes.
SWE-agent takes a GitHub issue and tries to automatically fix it, using your LM of choice. It can also be employed for offensive cybersecurity or competitive coding challenges. [NeurIPS 2024]
Docker Images definitions and utility scripts for rapid development and deployment of REDHAWK SDR systems, Domains, and Devices.
Espressif IoT Development Framework. Official development framework for Espressif SoCs.
A collection of learning resources for curious software engineers
Ref design combining the Zynq UltraScale+ MPSoC with the Hailo AI accelerator