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Starred repositories
RISC-V Formal Verification Framework
RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.
UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.
UVM + DPI-C reference model for PCIe Gen3 endpoint (transaction layer)
A synthesizer capable of transforming SVA properties into synthesizable hardware modules in Verilog register-transfer level (RTL).
usb-device implementation for Synopsys USB OTG IP cores
PCIe System Verilog Verification Environment developed for PCIe course
This project automates SOC workflows using Wazuh, Shuffle, and TheHive. It involves setting up a Windows 10 client with Sysmon and Ubuntu 22.04 for Wazuh and TheHive, deployed on cloud or VMs. Goal…
This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.
A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
General Purpose I/O agent written in UVM
This is literally a game framework, based on Unity game engine. It encapsulates commonly used game modules during development, and, to a large degree, standardises the process, enhances the develop…
This is literally a game framework, based on Unity game engine. It encapsulates commonly used game modules during development, and, to a large degree, standardises the process, enhances the develop…
Wavious DDR (WDDR) Physical interface (PHY) Hardware
Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM