ReText: Simple but powerful editor for Markdown and reStructuredText

the only cheat sheet you need

UVM AHB VIP

Simple command-line snippet manager

Package manager and build abstraction tool for FPGA/ASIC development

Python Filter Design Analysis Tool

Free Introduction to Bash Scripting eBook

The latest news, tutorials, and guides for DevOps professionals.

UltraZed Edition examples

A tui-based PDF viewer

Yet another vimrc

The largest Awesome Curated list of command line programs (CLI/TUI) with source data organized into CSV files

⭕ Share quick reference cheat sheet for developers.

Python-based IP-XACT parser

Common SystemVerilog RTL modules for RgGen

Control and status register code generator toolchain

UVM Testbench For SystemVerilog Combinator Implementation

Fork of Cadence's UVM 1.1 reference flow (modified by CVC)

This is the repository for the IEEE version of the book

Seamless navigation between tmux panes and vim splits

How to install Regolith on WSL2, with DPI support and launch files

Verilator open-source SystemVerilog simulator and lint system

Code generation tool for control and status registers

OpenTitan: Open source silicon root of trust

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

fake keyboard/mouse input, window management, and more

Verilog Ethernet components for FPGA implementation

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。