OpenROAD's unified application implementing an RTL-to-GDS Flow

Website of the Open Source Program Office, UC Santa Cruz

Logic synthesis and ABC based optimization

CROSS Repositories Web Site

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

A platform for managing machine learning experiments

dispatch.vim: Asynchronous build and test dispatcher

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

XLS: Accelerated HW Synthesis

ABC: System for Sequential Logic Synthesis and Formal Verification

https://caravel-user-project.readthedocs.io

Spectacle allows you to organize your windows without using a mouse.

A log4j vulnerability filesystem scanner and Go package for analyzing JAR files.

Python examples on Google Cloud Platform (GCP). How to manage Compute Engine VM instances, Cloud Storage buckets, etc.

The Runner for GitHub Actions 🚀

IDEA project source files

FPGA Design Suite based on C to Verilog design flow.