A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

Tools to make a HW designer's life easier

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:

Verilog AXI components for FPGA implementation

Hammer: Highly Agile Masks Made Effortlessly from RTL

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

AXI interface modules for Cocotb

Parallel Programming for FPGAs -- An open-source high-level synthesis book

This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

LLM-Aided FPGA Design for Signal Processing Applications

SAR ADC Analog IC simulation and layout for UNIC CASS 2024 held by IEEE Solid-State Circuits Society (SSCS)

An open source PDK using TIGFET 10nm devices.

An MLIR-based toolchain for AMD AI Engine-enabled devices.

HSPICE and MATLAB simulation files of a tracking SAR ADC

The root repo for lowRISC project and FPGA demos.

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

Website for the OpenROAD tutorial held at the MICRO 2022 conference

PicoRV32 - A Size-Optimized RISC-V CPU

Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.