DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. [This fork is only a mirror, not for development]

VexRiscv cpu on FPGA. [This fork is only a mirror, not for development]

Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface. [This fork is only a mirror, not for development]

BBC micro - Demistified for Deca & Neptuno. [This fork is only a mirror, not for development]

Atari ST/STe core demistyfied. See Readme in board folder (Deca, ...)

Repo that shows how to use the VexRiscv with OpenOCD and semihosting.

Dual 32 MB SDRAM + 2 MB SRAM MiSTer module with 3 extra pins for DECA retro cape 2

Template with latest framework for SoCkit (MiSTer)

Mega CD for Sockit (MiSTer)

Retro cape (addon) for DECA FPGA

The Terasic DECA board as a mandelbrot accelerator. [This fork is only a mirror, not for development]

PSX for SoCkit (MiSTer firmware)

NES for SoCkit (MiSTer firmware)

TurboGrafx-16 CD / PC Engine CD for SoCkit (MiSTer)

Memtest core for SoCkit board to test SDRAM MiSTer modules with GPIO addon

Sega Master System Sockit (MiSTer)

Cave 68K arcade classics for Sockit (Mister)

GBA for SoCkit (MiSTer firmware)

Gameboy for SoCkit (MiSTer firmware)

Absolute beginner's guide to the de10-nano [so it should apply to SoCKit as well]