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Starred repositories

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Custom chess engine playstyle for drilling opening, middlegame, and endgame. OAuth2.0 support, with plans to track rating performance and adjust difficulty to play strength.

TypeScript 4 Updated Mar 10, 2025

In this project, I explored how local LLMs can be used to label data and support analyses. Specifically, I used Llama2 model to automatically categorise my bank transaction data.

Jupyter Notebook 850 242 Updated May 16, 2024

A Golang Tool to discover unused Kubernetes Resources

Go 1,552 130 Updated Nov 23, 2025

Let's get it

Verilog 89 6 Updated Sep 18, 2022

An enterprise-class UI design language and React UI library

TypeScript 96,699 54,069 Updated Nov 25, 2025

Boltstream Live Video Streaming Website + Backend

Python 1,748 132 Updated Jun 14, 2021

Tool for making your CSV files ready to import into YNAB

JavaScript 185 91 Updated Sep 22, 2025

A web driver to download account activity .qfx files from Wells Fargo (for YNAB). Written in Python using Splinter.

Python 3 2 Updated Jan 7, 2024

A running-jumping-swordfighting game I made on the Apple II from 1985-89

Assembly 6,614 702 Updated Sep 27, 2024

Docker registry v2 command line client and repo listing generator with security checks.

Go 1,703 172 Updated Jun 25, 2024

Run Tailscale in the container on k8s

HTML 7 1 Updated Nov 6, 2020

Standalone, daemon-less, unprivileged Dockerfile and OCI compatible container image builder.

Go 3,982 234 Updated May 19, 2024

An Verilog implementation of a 16 bit processor, codenamed Artemis

Verilog 4 2 Updated Oct 21, 2020

Cluster monitoring stack for clusters based on Prometheus Operator

Jsonnet 754 201 Updated Aug 22, 2025

Create and render emails on the server with React

JavaScript 145 33 Updated Jun 10, 2021

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

Verilog 321 48 Updated Jan 12, 2018

CPU microarchitecture, step by step

Verilog 205 64 Updated Nov 1, 2020

v8cpu is a simple multi-cycle von Neumann architecture 8-bit CPU in under 500 lines of Verilog.

Verilog 14 3 Updated Feb 24, 2018

Implemetation of pipelined ARM7TDMI processor in Verilog

Verilog 90 25 Updated Apr 19, 2018

NES Emulator, and Tutorial Video Code

C++ 1,492 237 Updated Jan 9, 2024

A collection of questions to practice with for SRE interviews

972 224 Updated Jan 25, 2022

Site Reliability Engineer Interview Preparation Guide

8,528 2,196 Updated Nov 2, 2025

Dedicated Resources for the Low-Level System Design. Learn how to design and implement large-scale systems. Prep for the system design interview.

7,402 2,404 Updated Jan 1, 2024

An assembler, written in python, for the ARMv7-A architecture that features a simplified syntax

Python 2 Updated Dec 15, 2015

EvilVM compiler for information security research tools.

Assembly 204 21 Updated May 14, 2022

A fully integrated development environment for a mid-to-late 1980's arcade like hardware platform.

31 6 Updated Apr 8, 2019

Virtualize Rpi Arm Architecture with Qemu on OSX.

4 Updated May 12, 2019

Mirror of JONESFORTH

Assembly 1,087 154 Updated Apr 4, 2023

Tiny assembler for 8086/8088, able to run over DOS for 8086/8088 machines.

Assembly 205 15 Updated May 8, 2025

All code found on nandland is here. underconstruction.gif

Verilog 350 77 Updated Aug 21, 2022
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