Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Common SystemVerilog components

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现

Clio, ASPLOS'22.

A Fast, Low-Overhead On-chip Network

程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).

BaseJump STL: A Standard Template Library for SystemVerilog

GPT Meet Zotero.

A Linux-capable RISC-V multicore for and by the world

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

RSD: RISC-V Out-of-Order Superscalar Processor

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Like VexRiscv, but, Harder, Better, Faster, Stronger

A debugging and profiling tool that can trace and visualize python code execution

A simple AXI4 DMA unit written in SpinalHDL.

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

My SpinalHDL library intended to be reused across multiple HDL projects

Hammer: Highly Agile Masks Made Effortlessly from RTL

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Common building blocks for my SpinalHDL designs

Modular hardware build system

For v1.2 test

A FPGA friendly 32 bit RISC-V CPU implementation

Vitis_Accel_Examples

Vitis In-Depth Tutorials

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.