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Achievement: StarstruckAchievement: QuickdrawAchievement: Pull Sharkx2Achievement: YOLO

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skudlur/README.md

Hello there 👋

My name is Suhas Kudlur Viswanath and I develop RTL for accelerators, RISC-V processors and interconnects. I also like Rust and write tools to aid my research using it. At present, I am a Master's By Research candidate at The University of Edinburgh, School of Informatics working on improving memory locality and accessibility of applications that demand the use of multi-socket and multi-unit server systems.

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  1. dma-bsv dma-bsv Public

    Direct Memory Access Controller and Memory Interface

    Bluespec 6

  2. diablo diablo Public

    diablo is an Out-Of-Order 64-bit RISC-V processor.

    SystemVerilog 16 4

  3. cayde cayde Public

    cayde is 32-bit RISC-V core written in SystemVerilog

    SystemVerilog 8 8

  4. waveplot waveplot Public

    waveplot is a VCD waveform generator for the terminal.

    Rust 4 2

  5. RISCulator RISCulator Public

    RISCulator is a RISC-V emulator.

    Rust 12

  6. rv-decoder rv-decoder Public

    RISC-V Decoder library for Rust

    Rust 3 1