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scr1 Public
Forked from syntacore/scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog Other UpdatedDec 19, 2023 -
lab-riscv-asm Public
Laboratory work. Sum of elements of the row with the given number.
Assembly UpdatedDec 5, 2023 -
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simple_messenger Public
implementation of a simplest instant messaging system
C++ UpdatedMar 12, 2023 -
abstract_tree_generator Public
implementation of the simplest abstract syntax tree generator
C UpdatedMar 10, 2023 -
p2p-chat Public
implementation of a p2p chat using encryption to send messages
Erlang Apache License 2.0 UpdatedMar 7, 2023 -
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hashmap_separate_chain Public
hashmap separate chain implementation with basic functional on erlang
Erlang Apache License 2.0 UpdatedJan 16, 2023 -
erlang_euler_problems Public
solutions of 11 and 27 euler's problems on erlang
Erlang Apache License 2.0 UpdatedJan 11, 2023 -
arithmetic_rtl Public
implementation of a mathematical function at the RTL level using Verilog HDL.
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sega_splatterhouse_3_project Public
сompatible demo game with Sega Mega Drive 16 bit.
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course_work_backend Public
Backend of course work on information systems and databases. Application for lovers of extreme sports.
Java UpdatedMar 7, 2022 -
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low_level_programming Public
repository with laboratory works on the course "low-level programming" at ITMO University
Assembly UpdatedNov 26, 2021 -
electrostatic_field_simulator Public
Forked from stormrvge/ElectroStaticFieldSimulatorC++ UpdatedOct 18, 2021 -
riscv Public
Forked from zhelnio/schoolRISCVCPU microarchitecture, step by step
Makefile Other UpdatedSep 8, 2021 -
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raycasting Public
implementation of a simple raycasting system using the sfml library
C++ UpdatedMay 9, 2021 -
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