Skip to content
View poleguy's full-sized avatar

Block or report poleguy

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Asynchronous Web Opaque Objects

3 Updated Mar 11, 2022

Proton Pack Telemetry Capture System

Verilog 1 Updated Nov 8, 2025

Securely synchronize files with your devices on iOS using Syncthing

Swift 1,223 31 Updated Jan 12, 2026

Quick and simple security for Flask applications

Python 694 161 Updated Jan 12, 2026

Assorted KiCad Symbols and Footprints

OpenSCAD 13 4 Updated Dec 26, 2025

Enforce the habit of self-documenting code through better commit messages.

Go 231 6 Updated Dec 23, 2025

🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)

SystemVerilog 45 9 Updated Jul 16, 2021

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

C++ 97 29 Updated Jun 6, 2020

USB3 PIPE interface for Xilinx 7-Series

Verilog 240 39 Updated Jan 2, 2026

(Not Quite) the Worlds Worst Video Card

1 Updated Aug 13, 2025

SERV - The SErial RISC-V CPU

Verilog 1,729 242 Updated Jan 5, 2026

code to position motor based on backEMF and speed accumulation

C 17 1 Updated Dec 3, 2023

1 bit ADC that frames result as serial data. Play the audio with a lowpass on TxD.

C 22 1 Updated May 4, 2024

Educated Guess Motor Kicking, the new, revolutionary position control method thats name is cooler than PID

C 9 1 Updated Nov 28, 2025

A Mozilla Firefox extension. A useful tool for web links.

JavaScript 36 10 Updated Nov 4, 2021

the NSA selector eurorack module

Python 165 5 Updated Oct 25, 2025

Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.

Verilog 40 8 Updated Apr 13, 2021

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog 410 95 Updated Sep 16, 2025

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

SystemVerilog 569 95 Updated Jan 12, 2026

Unofficial Python security updates for Windows

832 97 Updated Dec 30, 2025

Export Microsoft Teams Chats to a local HTML file

PowerShell 95 23 Updated Jul 26, 2025

OpenBao exists to provide a software solution to manage, store, and distribute sensitive data including secrets, certificates, and keys.

Go 5,203 307 Updated Jan 12, 2026

Android app to open CherryTree databases

Java 106 4 Updated Aug 28, 2025

A Mastodon to POP3 Gateway

Rust 170 5 Updated Dec 24, 2023

Xash3D FWGS engine

C 2,284 369 Updated Jan 13, 2026

Single Packet Authorization > Port Knocking

Perl 1,283 248 Updated Nov 26, 2025

A python library built to empower developers to build applications and systems with self-contained Computer Vision capabilities

Python 8,849 2,207 Updated Aug 3, 2024

PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.

C++ 27 6 Updated Dec 22, 2025

An RFC791 form for the analogue sending of digital traffic.

4 Updated Dec 26, 2024
Next