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Commits on Nov 11, 2025

• [RISCV] Set __GCC_CONSTRUCTIVE_SIZE/__GCC_DESTRUCTIVE_SIZE to 64 (#162986)

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Commits on Sep 12, 2025

• [RISCV] Move MachineCombiner to addILPOpts() (#158071)

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Commits on Aug 21, 2025

• [RISCV] Optimize the spill/reload of segment registers (#153184)

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Commits on Jul 31, 2025

• [RISCV][NFC] Rename memset tests (#151486)

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Commits on Jul 30, 2025

• [RISCV] Support PreserveMost calling convention (#148214)

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Commits on Jul 10, 2025

• [RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)

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Commits on Jun 18, 2025

• [RISCV] Support non-power-of-2 types when expanding memcmp

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Commits on Jun 17, 2025

• [TargetParser] Increase MAX_SUBTARGET_FEATURES to 384 (#144326)

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Commits on Jun 13, 2025

• [RISCV] Support memcmp expansion for vectors

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Commits on Jun 12, 2025

• [RISCV] Get host CPU name via hwprobe (#142745)

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Commits on Jun 3, 2025

• [RISCV][NFC] Simplify the creation of Scheduler (#142553)

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• [MISched] Add templates for creating custom schedulers (#141935)

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Commits on May 19, 2025

• [RISCV][NFC] Fix the mismatch in comment (#140511)

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Commits on May 13, 2025

• [TableGen][MacroFusion] Predicate if the first inst has the same register (#137778)

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Commits on May 12, 2025

• [RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)

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Commits on Apr 30, 2025

• [RISCV][NFC] Convert some predicates to TIIPredicate (#129658)

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Commits on Apr 27, 2025

• [RISCV][NFC] Remove attributes in pr107950.ll (#137500)

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• [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (#136842)

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Commits on Apr 18, 2025

• [RISCV][NFC] Add Zicsr to profiles explicitly (#136134)

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Commits on Apr 14, 2025

• [RISCV][NFC] Use bitmasks generated by TableGen

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• [RISCV] Add missing bitmask for some extensions (#135599)

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• [mailmap] Update my name

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• [RISCV][NFC] Make generated intrinsic records more human-readable (#133710)

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• Revert "[RISCV][NFC] Make generated intrinsic records more human-readable (#133710)"

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• [RISCV][NFC] Make generated intrinsic records more human-readable (#133710)

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Commits on Apr 3, 2025

• [TableGen] Emit `llvm::is_contained` for `CheckOpcode` predicate (#134057)

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Commits on Mar 28, 2025

• [TableGen] Add `!instances` operator to get defined records (#129680)

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• [RISCV] Don't vectorize for loops with small trip count (#132176)

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Commits on Mar 13, 2025

• [RegAlloc] Scale the spill weight by target factor (#113675)

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• [TableGen] Add `!match` operator to do regex matching (#130759)

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Commits on Mar 11, 2025

• [RISCV] Enable prefetching writes (#130561)

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Commits on Feb 18, 2025

• [RISCV] Implement isHighLatencyDef() (#127476)

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Commits on Feb 14, 2025

• [RISCV] Add a generic OOO CPU (#120712)

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Commits on Feb 13, 2025

• [RISCV][NFC] Move GenericModel to standalone file (#127003)

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Commits on Feb 5, 2025

• [RISCV] Enable RVV ABD tests with i64 elements (#124246)

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