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verilog-axis Public
Forked from alexforencich/verilog-axisVerilog AXI stream components for FPGA implementation
Python MIT License UpdatedApr 23, 2024 -
verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedNov 11, 2023 -
HDLGen Public
Forked from WilsonChen003/HDLGenHDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Verilog UpdatedOct 6, 2023 -
SpinalHDL_CNN_Accelerator Public
CNN accelerator implemented with Spinal HDL
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