linien-org · bleykauf · Feb 21, 2023 · Jun 2, 2022 · Jun 2, 2022 · Jun 2, 2022
diff --git a/.github/workflows/pyinstaller-linux2.yml b/.github/workflows/pyinstaller-linux2.yml
@@ -0,0 +1,47 @@
+name: Pyinstaller Linux (new)
+
+on:
+  workflow_dispatch:
+
+env:
+  QT_DEBUG_PLUGINS: 1
+  DISPLAY: ":99"
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          fetch-depth: 0
+
+      - name: Set up Python
+        uses: actions/setup-python@v4
+        with:
+          python-version: "3.7"
+
+      - name: Install dependencies
+        run: sudo apt-get install -y qt5-default qttools5-dev-tools binutils libxkbcommon-x11-0 libxcb-icccm4 libxcb-image0 libxcb-keysyms1 libxcb-randr0 libxcb-render-util0 libxcb-xinerama0 libxcb-xfixes0 libegl1-mesa
+
+      - run: pip install pyinstaller
+
+      - name: Install linien-common
+        working-directory: linien-common
+        run: pip install .
+
+      - name: Install linien-client
+        working-directory: linien-client
+        run: pip install .
+
+      - name: Install linien-gui
+        working-directory: linien-gui
+        run: pip install .
+
+      - run: pyinstaller pyinstaller.spec
+        working-directory: linien-gui
+
+      - uses: actions/upload-artifact@v3
+        with:
+          name: linien-gui-linux
+          path: linien-gui/dist/*
diff --git a/.github/workflows/pyinstaller-windows.yml b/.github/workflows/pyinstaller-windows.yml
@@ -1,43 +1,30 @@
 name: Pyinstaller Windows
 
 on:
-  # Allows you to run this workflow manually from the Actions tab
   workflow_dispatch:
-    inputs:
-      version_name:
-        description: "Version name"
-        required: true
 
-env:
-  INPUT_VERSION_NAME: ${{ github.event.inputs.version_name }}
-
-# A workflow run is made up of one or more jobs that can run sequentially or in parallel
 jobs:
-  # This workflow contains a single job called "build"
   build:
-    # The type of runner that the job will run on
     runs-on: ubuntu-latest
 
-    # Steps represent a sequence of tasks that will be executed as part of the job
     steps:
-      # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
       - uses: actions/checkout@v2
 
-      - name: create VERSION file
-        run: echo "$INPUT_VERSION_NAME" > linien/VERSION
-
-      # NOTE: we hardcode the version of requirements here because the new pip
-      #       resolver otherwise takes ages
-      # ANOTHER NOTE: scipy is fixed to 1.4.1 because of problems with pyinstaller
-      - name: create requirements file
-        run: cp requirements_gui.txt requirements.txt
+      - name: Set up Python
+        uses: actions/setup-python@v2
+        with:
+          python-version: "3.x"
+      - name: Install dependencies
+        run: |
+          python -m pip install --upgrade pip
+          pip install setuptools wheel twine
 
       - name: PyInstaller Windows
         uses: JackMcKew/pyinstaller-action-windows@main
         with:
-          path: .
+          path: linien-gui
 
       - uses: actions/upload-artifact@v2
         with:
           name: my-exe
-          path: dist/windows
+          path: linien-gui/dist/windows
diff --git a/.github/workflows/pyinstaller-windows2.yml b/.github/workflows/pyinstaller-windows2.yml
@@ -0,0 +1,40 @@
+name: Pyinstaller Windows (new)
+
+on:
+  workflow_dispatch:
+
+jobs:
+  build:
+    runs-on: windows-latest
+
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          fetch-depth: 0
+
+      - name: Set up Python
+        uses: actions/setup-python@v4
+        with:
+          python-version: "3.7"
+
+      - run: pip install pyinstaller
+
+      - name: Install linien-common
+        working-directory: linien-common
+        run: pip install .
+
+      - name: Install linien-client
+        working-directory: linien-client
+        run: pip install .
+
+      - name: Install linien-gui
+        working-directory: linien-gui
+        run: pip install .
+
+      - run: pyinstaller pyinstaller.spec
+        working-directory: linien-gui
+
+      - uses: actions/upload-artifact@v3
+        with:
+          name: linien-gui-windows
+          path: linien-gui/dist/*
diff --git a/.gitignore b/.gitignore
@@ -9,7 +9,6 @@ __pycache__
 /*.v
 /dist
 .eggs
-linien-*
 
 .mypy_cache
 .vscode
@@ -23,4 +22,26 @@ VERSION
 
 # results of pytest-html
 tests/*.html
-tests/assets/*
+tests/assets/*
+
+# Distribution / packaging
+.Python
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+share/python-wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+MANIFEST
+
+**/_version.py
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
@@ -1,13 +1,12 @@
 repos:
   - repo: https://github.com/psf/black
-    rev: 22.10.0
+    rev: 23.1.0
     hooks:
       - id: black
-        language_version: python3.7
         exclude: ^(gateware/logic/|gateware/lowlevel/|linien/server/csrmap.py)
 
   - repo: https://github.com/pycqa/isort
-    rev: 5.10.1
+    rev: 5.12.0
     hooks:
       - id: isort
         name: isort (python)
diff --git a/MANIFEST.in b/MANIFEST.in
diff --git a/README.md b/README.md
@@ -200,7 +200,8 @@ Then, you should start the Linien server on your RedPitaya. This can be done by
 
 Once the server is up and running, you can connect using python:
 ```python
-from linien.client.connection import LinienClient, MHz, Vpp
+from linien_client.connection import LinienClient
+from linien_common.common import  MHz, Vpp
 c = LinienClient(
     {'host': 'rp-XXXXXX.local', 'username': 'root', 'password': 'change-it-to-something-else!'},
     # starts the server if it is not running
@@ -288,8 +289,8 @@ The script below shows an example of how to run the autolock using the scripting
 import pickle
 import numpy as np
 
-from linien.client.connection import LinienClient
-from linien.common import FAST_AUTOLOCK
+from linien_client.connection import LinienClient
+from linien_common.common import FAST_AUTOLOCK
 
 from matplotlib import pyplot as plt
 from time import sleep

diff --git a/scripts/bit2bin.py → gateware/bit2bin.py b/scripts/bit2bin.py → gateware/bit2bin.py
diff --git a/scripts/build_fpga_image.sh → gateware/build_fpga_image.sh b/scripts/build_fpga_image.sh → gateware/build_fpga_image.sh
@@ -14,7 +14,5 @@ fi
 
 export PATH=$VIVADOPATH:$PATH
 
-python3 scripts/fpga_image_helper.py
-
-rm linien/server/linien.bin -f
-cp fpga_build/linien.bin linien/server
+rm linien-server/linien_server/linien.bin -f
+python3 gateware/fpga_image_helper.py
diff --git a/scripts/fpga_image_helper.py → gateware/fpga_image_helper.py b/scripts/fpga_image_helper.py → gateware/fpga_image_helper.py
@@ -18,19 +18,13 @@
 
 # this file compiles the FPGA image. You shouldn't call it directly though but
 # use `build_fpga_image.sh`
-import os
-import sys
+from pathlib import Path
 
-LINIEN_FOLDER = "/".join(os.path.abspath(__file__).split("/")[:-2])
-
-
-os.chdir(LINIEN_FOLDER)
-sys.path.append(LINIEN_FOLDER)
+REPO_ROOT_DIR = Path(__file__).resolve().parents[1]
 
 from bit2bin import bit2bin
-
-from gateware.linien import RootModule
-from gateware.platform import Platform
+from hw_platform import Platform
+from linien_module import RootModule
 
 
 def py_csrconstants(map, fil):
@@ -66,14 +60,20 @@ def py_csrmap(it, fil):
     platform = Platform()
     root = RootModule(platform)
 
-    with open("linien/server/csrmap.py", "w") as fil:
+    with open(
+        REPO_ROOT_DIR / "linien-server" / "linien_server" / "csrmap.py", "w"
+    ) as fil:
         py_csrconstants(root.linien.csrbanks.constants, fil)
         csr = get_csrmap(root.linien.csrbanks.banks)
         py_csrmap(csr, fil)
         fil.write("states = {}\n".format(repr(root.linien.state_names)))
         fil.write("signals = {}\n".format(repr(root.linien.signal_names)))
 
-    platform.add_source_dir("verilog")
-    build_dir = "fpga_build"
+    platform.add_source_dir(REPO_ROOT_DIR / "gateware" / "verilog")
+    build_dir = REPO_ROOT_DIR / "gateware" / "build"
     platform.build(root, build_name="top", build_dir=build_dir)
-    bit2bin("%s/top.bit" % build_dir, "%s/linien.bin" % build_dir, flip=True)
+    bit2bin(
+        build_dir / "top.bit",
+        REPO_ROOT_DIR / "linien-server" / "linien_server" / "linien.bin",
+        flip=True,
+    )
diff --git a/gateware/platform.py → gateware/hw_platform.py b/gateware/platform.py → gateware/hw_platform.py
@@ -172,7 +172,7 @@ class Platform(XilinxPlatform):
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, toolchain="vivado")
         self.toolchain.pre_synthesis_commands.append(
-            "read_xdc -ref processing_system7_v5_4_processing_system7 ../verilog/system_processing_system7_0_0.xdc"
+            "read_xdc -ref processing_system7_v5_4_processing_system7 ../verilog/system_processing_system7_0_0.xdc"  # noqa: E501
         )
         self.toolchain.with_phys_opt = True
 
@@ -188,7 +188,7 @@ def do_finalize(self, fragment):
             )
             for i in range(2):
                 try:
-                    adc = self.lookup_request("adc", i)
+                    _ = self.lookup_request("adc", i)
                     # self.add_platform_command("set_input_delay "
                     #    "-clock {clk} 3.4 [get_ports {data}]",
                     #    clk=clk125, data=adc[0])

diff --git a/gateware/linien.py → gateware/linien_module.py b/gateware/linien.py → gateware/linien_module.py
@@ -17,6 +17,7 @@
 # You should have received a copy of the GNU General Public License
 # along with Linien.  If not, see <http://www.gnu.org/licenses/>.
 
+from linien_common.common import ANALOG_OUT0
 from migen import (
     Array,
     Cat,
@@ -31,9 +32,7 @@
 from misoc.interconnect import csr_bus
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
 
-from gateware.logic.autolock import FPGAAutolock
-from linien.common import ANALOG_OUT0
-
+from .logic.autolock import FPGAAutolock
 from .logic.chains import FastChain, SlowChain, cross_connect
 from .logic.decimation import Decimate
 from .logic.delta_sigma import DeltaSigma

diff --git a/gateware/logic/autolock.py b/gateware/logic/autolock.py
@@ -16,11 +16,15 @@
 # You should have received a copy of the GNU General Public License
 # along with Linien.  If not, see <http://www.gnu.org/licenses/>.
 
+from linien_common.common import (
+    AUTOLOCK_MAX_N_INSTRUCTIONS,
+    FAST_AUTOLOCK,
+    ROBUST_AUTOLOCK,
+)
 from migen import Array, If, Module, Signal, bits_for
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
 
-from gateware.logic.autolock_utils import SumDiffCalculator
-from linien.common import AUTOLOCK_MAX_N_INSTRUCTIONS, FAST_AUTOLOCK, ROBUST_AUTOLOCK
+from .autolock_utils import SumDiffCalculator
 
 ROBUST_AUTOLOCK_FPGA_DELAY = 3
 

diff --git a/verilog/axi_slave.v → gateware/verilog/axi_slave.v b/verilog/axi_slave.v → gateware/verilog/axi_slave.v
diff --git a/verilog/bus_clk_bridge.v → gateware/verilog/bus_clk_bridge.v b/verilog/bus_clk_bridge.v → gateware/verilog/bus_clk_bridge.v
diff --git a/...cessing_system7_v5_4_processing_system7.v → ...cessing_system7_v5_4_processing_system7.v b/...cessing_system7_v5_4_processing_system7.v → ...cessing_system7_v5_4_processing_system7.v
diff --git a/verilog/red_pitaya_scope.v → gateware/verilog/red_pitaya_scope.v b/verilog/red_pitaya_scope.v → gateware/verilog/red_pitaya_scope.v
diff --git a/verilog/system_processing_system7_0_0.v → ...e/verilog/system_processing_system7_0_0.v b/verilog/system_processing_system7_0_0.v → ...e/verilog/system_processing_system7_0_0.v
diff --git a/verilog/system_processing_system7_0_0.xdc → ...verilog/system_processing_system7_0_0.xdc b/verilog/system_processing_system7_0_0.xdc → ...verilog/system_processing_system7_0_0.xdc
diff --git a/linien-client/linien_client/__init__.py b/linien-client/linien_client/__init__.py
@@ -0,0 +1 @@
+from ._version import __version__  # noqa: F401