SystemVerilog frontend for Yosys

A tool for analysing the source-level static connectivity of a SystemVerilog design

SystemVerilog compiler and language services

Quip Automation REST API for editing documents, folders, and users

Playwright MCP server

Browser MCP is a Model Context Provider (MCP) server that allows AI applications to control your browser

HDL symbol generator

SystemVerilog parser library fully compliant with IEEE 1800-2017

Native Pager in SwiftUI

An abstraction library for interfacing EDA tools

AHA! Website Source

CaDiCaL SAT Solver

List of awesome open source hardware tools, generators, and reusable designs

NeuroSAT: Learning a SAT Solver from Single-Bit Supervision

OpenTitan: Open source silicon root of trust

Bus bridges and other odds and ends

Fixed Point Math Library for Verilog

An efficient minimal perfect hash function generator for small sets

An Open-source FPGA IP Generator

Caliptra IP and firmware for integrated Root of Trust block

Automatic SystemVerilog linting in github actions with the help of Verible

Verilog library for ASIC and FPGA designers

SVA examples and demonstration

Digital timing diagram editor

Tools for working with circuits as graphs in python

📚 A curated list of papers for Software Engineers