RSD: RISC-V Out-of-Order Superscalar Processor

wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.

Hardware Description Languages

An Open-source FPGA IP Generator

A parser for KLayout layer properties files (*.lyp)

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

An unofficial implementation of the SRDS algorithm

Mt-KaHyPar (Multi-Threaded Karlsruhe Hypergraph Partitioner) is a shared-memory multilevel graph and hypergraph partitioner equipped with parallel implementations of techniques used in the best seq…

An open source graphics editor for 2025: comprehensive 2D content creation tool suite for graphic design, digital art, and interactive real-time motion graphics — featuring node-based procedural ed…

A submodule of Chipyard https://github.com/ucb-bar/chipyard

Hardware Hierarchical Dynamic Structures

Tesseract Open Source OCR Engine (main repository)

Sophia means "wisdom" in Greek

Spell checker for neovim

21st century electronic design automation tools, written in Rust.

TheBoringNotch: Not so boring notch That Rocks 🎸🎶

Rust library for writing waveform traces in the FST format.

The HW-CBMC and EBMC Model Checkers for Verilog

Sequential Logic

SystemVerilog frontend for Yosys

Website for CS 265

A standalone implementation of the Tethered Serial Interface (TSI) in Python.

Chisel RISC-V Vector 1.0 Implementation