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🎧☁️ Your Personal Streaming Service

Go 18,444 1,315 Updated Jan 8, 2026

An open source and lightweight music client for Subsonic, designed and built natively for Android.

Java 528 45 Updated Jan 10, 2026

The Free Software Media System - Server Backend & API

C# 47,527 4,296 Updated Jan 10, 2026

High performance self-hosted photo and video management solution.

TypeScript 88,737 4,705 Updated Jan 10, 2026

Install Jellyfin on your Samsung TV

Shell 1,374 73 Updated Oct 31, 2025

Style guide enforcement for VHDL

Python 230 60 Updated Jan 1, 2026

Opensource DDR3 Controller

Verilog 406 58 Updated Dec 31, 2025

10Gb Ethernet Switch

C 247 31 Updated Oct 16, 2025

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Verilog 1,291 31 Updated Jan 6, 2026

AXI interface modules for Cocotb

Python 305 100 Updated Sep 30, 2025

The music player of today! 🌇

Python 2,397 100 Updated Jan 10, 2026

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

SystemVerilog 567 95 Updated Jan 2, 2026

GUI file synchronization client that can sync with any cloud provider

Rust 1,609 56 Updated Nov 21, 2025

Ethernet interface modules for Cocotb

Python 73 24 Updated Sep 8, 2025

Basic ECP5 based GigE to SYZYGY interface.

HTML 209 20 Updated Sep 18, 2023

Create database files for the genealogytree LaTeX package from GEDCOM files

Python 11 2 Updated Mar 11, 2025

Open Logic FPGA Standard Library

VHDL 841 92 Updated Jan 9, 2026

Rich is a Python library for rich text and beautiful formatting in the terminal.

Python 55,082 1,993 Updated Dec 22, 2025

Universal utility for programming FPGA

C++ 1,516 313 Updated Jan 8, 2026

Portable HyperRAM controller

VHDL 62 14 Updated Dec 8, 2024

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

SystemVerilog 69 14 Updated Dec 17, 2025

Unit testing for cocotb

Python 165 85 Updated Dec 6, 2025

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

VHDL 478 40 Updated Oct 21, 2025

Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board

C++ 32 2 Updated May 15, 2023

Testbed for testing NetFlow/IPFIX network monitoring probes. Includes tools for PCAP generation and replay of 1/10/100G network traffic.

C++ 53 5 Updated Dec 10, 2025

LGBM2VHDL: Tool for converting LightGBM models into VHDL implementation.

Python 6 2 Updated Dec 21, 2023

Source code for Gramps Genealogical program

Python 2,771 495 Updated Jan 10, 2026

LED blink example design for the Arrow DECA FPGA board

Shell 16 1 Updated Jul 30, 2021

FPGA cards files for the NDK

VHDL 3 1 Updated Oct 2, 2024
SystemVerilog 18 7 Updated Jul 3, 2025
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