FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository

An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs

TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.