Simple project to explore generating IP starting with Vitis HLS and migrating to Vivado for simulation.

A Tutorial on Putting High-Level Synthesis cores in PYNQ

Framework for FPGA-accelerated Middlebox Development

Research paper list for host networking: in a system view

A comprehensive open-source cache trace dataset

FB+-tree: A Memory-Optimized B+-tree with Latch-Free Update

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

A collection of Twitter's anonymized production cache traces.

UDP encrypt and decrypt example with pre-built network layer and cmac kernels

100 Gbps TCP/IP stack for Vitis shells

Open source FPGA-based NIC and platform for in-network compute

ESnet SmartNIC hardware design repository.

YCSB written in C++ for embedded databases. (supporting LevelDB, RocksDB, LMDB, WiredTiger, and SQLite)

VNx: Vitis Network Examples

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

Linux kernel source tree

计算机自学指南

Beta release of Masstree.

Multicore in-memory storage engine

MICA: A Fast In-memory Key-Value Store (see isca2015 branch for the ISCA2015 version)