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hemanth028/README.md

Hi there 👋, Myself HEMANTH S

RTL Design and Verification Engineer , India!

👨‍💻 About Me

  • 🎯 RTL Design and Verification Enthusiast
  • 📚 Bachelor's in Electronics and Communication Engineering (2023–2027)*
  • 🏫 Sri sivasubramaniya nadar college of engineering (SSN)

🛠 Skills

  • RTL Design: Verilog, SystemVerilog
  • Programming: C++, Python

🎯 Fields of Interest

  • VLSI
  • RTL Design and Verification
    --

📫 Contact

Popular repositories Loading

  1. Verilog-codes Verilog-codes Public

    Verilog 2

  2. UART-protocol-using-verilog UART-protocol-using-verilog Public

    Implementation of UART protocol using verilog on Nexys A7 100T FGPA board

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  3. FPGA_Mini_Projects FPGA_Mini_Projects Public

    This repository contains a collection of FPGA projects ranging from beginner to advanced levels, documenting my learning journey in digital design and hardware development.

    Verilog

  4. hemanth028 hemanth028 Public

  5. riscv-single-cycle-processor riscv-single-cycle-processor Public

    Forked from sabarishmohanjs/riscv-single-cycle-processor

    A Verilog implementation of a RISC-V single-cycle processor

    Verilog