omniverse simulation for f1tenth racing

대항해시대2를 웹으로 편하게 즐기자!

Testing memory-level parallelism

The Google Scholar PDF Reader browser extension, now with annotations!

A tool for decomposing DRAM address mapping into component-level functions

Introduction to Machine Learning Systems

[ICCV 2019] TSM: Temporal Shift Module for Efficient Video Understanding

A docker file for rerunning simulations in detmem

A heterogeneous architecture timing model simulator.

Linux sources

Real-Time Gang Scheduling in Linux

Model-predictive control for microcontrollers (fork mapping tinyMPC to gemmini or other HW accelerators)

TinyMPC-integrated firmware for the Crazyflie Nano Quadcopter

Code from the paper "Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters", with updates for Kaby Lake CPUs

LLM101n: Let's build a Storyteller

A tiny scalar-valued autograd engine and a neural net library on top of it with PyTorch-like API

BLISlab: A Sandbox for Optimizing GEMM

This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configur…

educational image sharing website built on a combination of modern C++, web and database technologies

[ICML 2024 Oral] Any-Precision LLM: Low-Cost Deployment of Multiple, Different-Sized LLMs

Neural Networks with low bit weights on low end 32 bit microcontrollers such as the CH32V003 RISC-V Microcontroller and others

Labs for the EE292D Edge ML class at Stanford

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

[TMLR 2024] Efficient Large Language Models: A Survey