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Learning
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University of Chinese Academy of Sciences
- Beijing
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16:56
(UTC +08:00)
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OpenXiangShan/XiangShan
OpenXiangShan/XiangShan PublicOpen-source high-performance RISC-V processor
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ibex
ibex PublicForked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog
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chipyard
chipyard PublicForked from ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Scala
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