Highlights
- Pro
Lists (13)
Sort Name ascending (A-Z)
- All languages
- AGS Script
- Alloy
- Assembly
- AutoIt
- Bluespec
- Brainfuck
- C
- C#
- C++
- CMake
- CSS
- Common Lisp
- Coq
- Cuda
- D
- Dart
- Dockerfile
- Emacs Lisp
- Erlang
- Fortran
- GLSL
- Gnuplot
- Go
- HTML
- Haskell
- Java
- JavaScript
- Jupyter Notebook
- LLVM
- Lua
- MATLAB
- MLIR
- Makefile
- Markdown
- Mathematica
- Nim
- Nix
- OCaml
- Objective-C
- OpenQASM
- PHP
- Perl
- Python
- RPM Spec
- ReScript
- RobotFramework
- Rocq Prover
- Roff
- Ruby
- Rust
- SCSS
- Sail
- Scala
- Shell
- SourcePawn
- Svelte
- Swift
- SystemVerilog
- Tcl
- TeX
- TypeScript
- V
- VHDL
- Verilog
- Vim Script
- Zig
- nesC
Starred repositories
verilog-meetup / systemverilog-microarchitecture-challenge-for-ai-2
Forked from verilog-meetup/systemverilog-microarchitecture-challenge-for-ai-1SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.
repository for chipyard micro learning course
Maid is a cross-platform Flutter app for interfacing with GGUF / llama.cpp models locally, and with Ollama and OpenAI models remotely.
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
This repository contains the design and source code for an Out-of-Order (OOO) RISC-V implementation.
A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies
Description of a RISC-V architecture based on MIPS 3000
A Python-based C compiler for x86-64, featuring full parsing, semantic analysis, IR generation, and assembly code emission.
SPIR-V fragment shader GPU core based on RISC-V
User-friendly AI Interface (Supports Ollama, OpenAI API, ...)
A collection of ROM images with tests that will aid you in developing your own CHIP-8, SUPER-CHIP or XO-CHIP interpreter (or "emulator")
A 256-RISC-V-core system with low-latency access into shared L1 memory.
🐉 Making Rust a first-class language and ecosystem for GPU shaders 🚧
Khronos-reference front end for GLSL/ESSL, partial front end for HLSL, and a SPIR-V generator.
The Tensor Algebra Compiler (taco) computes sparse tensor expressions on CPUs and GPUs
VIP cheatsheet for Stanford's CME 295 Transformers and Large Language Models
A light-weight hardware oriented synchronous stream cipher.
An rv32i inspired ISA, SIMT GPU implementation in system-verilog.
2D Graphic Library optimized for Cortex-M processors
Cross-platform NES Emulator built with Dart and Flutter
Multi-system emulator (NES, SNES, GB, GBA, PCE, SMS/GG, WS) for Windows, Linux and macOS
A Chisel verison of the tiny-gpu project, with more verification codes than original implementation
Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
A minimal GPU design in Verilog to learn how GPUs work from the ground up