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SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.

SystemVerilog 21 4 Updated Sep 4, 2025

repository for chipyard micro learning course

HTML 7 9 Updated Jun 20, 2025

Maid is a cross-platform Flutter app for interfacing with GGUF / llama.cpp models locally, and with Ollama and OpenAI models remotely.

Dart 2,162 221 Updated Jul 28, 2025

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Scala 215 36 Updated Jan 23, 2020

This repository contains the design and source code for an Out-of-Order (OOO) RISC-V implementation.

SystemVerilog 4 Updated Apr 13, 2025

A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies

C++ 5 1 Updated May 27, 2025

A super-scalar Core based on RISCV in systemC

C++ 6 2 Updated Jan 29, 2023

Description of a RISC-V architecture based on MIPS 3000

C++ 13 7 Updated Apr 24, 2023
12 3 Updated Sep 2, 2025

A Python-based C compiler for x86-64, featuring full parsing, semantic analysis, IR generation, and assembly code emission.

Python 23 Updated Sep 10, 2025

SPIR-V fragment shader GPU core based on RISC-V

Verilog 42 12 Updated May 26, 2021

Main Web Site (Online Books)

HTML 9,833 948 Updated Apr 28, 2025

User-friendly AI Interface (Supports Ollama, OpenAI API, ...)

JavaScript 112,255 15,529 Updated Oct 11, 2025

A collection of ROM images with tests that will aid you in developing your own CHIP-8, SUPER-CHIP or XO-CHIP interpreter (or "emulator")

Roff 573 11 Updated Oct 12, 2025

A 256-RISC-V-core system with low-latency access into shared L1 memory.

C 306 57 Updated Oct 9, 2025

🐉 Making Rust a first-class language and ecosystem for GPU shaders 🚧

Rust 2,401 75 Updated Oct 12, 2025

Khronos-reference front end for GLSL/ESSL, partial front end for HLSL, and a SPIR-V generator.

C++ 3,350 918 Updated Oct 13, 2025

The Tensor Algebra Compiler (taco) computes sparse tensor expressions on CPUs and GPUs

C++ 1,325 195 Updated Apr 14, 2025

VIP cheatsheet for Stanford's CME 295 Transformers and Large Language Models

3,178 427 Updated Jul 27, 2025

A light-weight hardware oriented synchronous stream cipher.

Verilog 10 1 Updated Mar 19, 2022
C++ 59 12 Updated Oct 12, 2025
SystemVerilog 208 65 Updated Mar 6, 2025

An rv32i inspired ISA, SIMT GPU implementation in system-verilog.

C++ 206 7 Updated Feb 11, 2025

2D Graphic Library optimized for Cortex-M processors

C 362 83 Updated Sep 24, 2025

Cross-platform NES Emulator built with Dart and Flutter

Dart 54 2 Updated Oct 13, 2025

Multi-system emulator (NES, SNES, GB, GBA, PCE, SMS/GG, WS) for Windows, Linux and macOS

C++ 1,886 196 Updated Jul 16, 2025

A Chisel verison of the tiny-gpu project, with more verification codes than original implementation

Scala 8 2 Updated Jan 22, 2025

Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.

SystemVerilog 16 5 Updated Feb 26, 2023

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

SystemVerilog 51 12 Updated Jul 14, 2021

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 8,786 686 Updated Aug 18, 2024
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