Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Tired of pushing to test your .gitlab-ci.yml?

Open-source FPGA retro emulation handheld

Async/await reactive tools for Python 3.10+

OpenXuantie - OpenC906 Core

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

visual6502 remixed

Video Stream Scaler

Verilog modules required to get the OV7670 camera working

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

Drop In USB CDC ACM core for iCE40 FPGA

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

SpinalHDL Hardware Math Library

Jargon from the functional programming world in simple terms!

Documenting the Xilinx 7-series bit-stream format.

An Open Source ESP32 board for connecting to HUB75 Matrix Panels

A Rust embedded HAL crate for LiteX cores

Blue noise stippling in Processing

9p library for arduino

Online OR1K Emulator running Linux

draws an SVG schematic from a JSON netlist

Modular visual interface for GDB in Python

Various HDL (Verilog) IP Cores

Synchronous multiroom audio player

WIP snapclient on ESP32

YM2151 clone in verilog. FPGA proven.

Read the wired or wireless mbus protocol to acquire utility meter readings.