userspace stack switching toolkit handcoded in assembly

RISC-V hypervisor written in Rust

🤖 Just a command runner

RISC-V OS written in Rust

The Rust Performance Book

Parser and generator for the Diosix Manifest File System, which contains assets to load from firmware during startup

A `cargo` wrapper that executes a post build script after a successful build.

This repo hosts my personal diodesign.org website

The special README file for my GitHub profile

Print to Qemu's RISC-V virt serial port

FuseSoC-based SoC for VeeR EH1 and EL2

OpenTitan: Open source silicon root of trust

Windows kernel hacking framework, driver template, hypervisor and API written on C++

Examples for JFPatch as a service

Byte and word access to memory

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

3D Space Invaders game in Rust

Read and write device tree blob (DTB) data

A Python Interpreter written in Rust

Diosix platform-specific code for RISC-V systems

A tiny Open POWER ISA softcore written in VHDL 2008

Empowering everyone to build reliable and efficient software.

A directory of Western Digital’s RISC-V SweRV Cores

ARCHIVED: Modern Hypervisor for the Cloud. See https://github.com/cloud-hypervisor/cloud-hypervisor instead

A Rust-based, lightweight unikernel.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Calculate hole cards opponent(s) need to beat you in a given Texas Hold 'em hand

Keep it simple, stupid 3d graphics engine for Rust.

A news feed headline aggregator for journalists and news junkies.