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darktable is an open source photography workflow application and raw developer

C 11,656 1,256 Updated Nov 25, 2025

vivado non-project example

Tcl 4 4 Updated Sep 20, 2018

Algorithmic C Math Library

C++ 65 19 Updated Nov 14, 2025

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

Verilog 56 9 Updated Sep 15, 2020

Robust Stereo Visual Inertial Odometry for Fast Autonomous Flight

C++ 1,884 611 Updated Nov 22, 2023

An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.

SystemVerilog 397 40 Updated Mar 11, 2023
HTML 7 1 Updated Feb 6, 2020

Simple single-port AXI memory interface

SystemVerilog 47 28 Updated Jun 7, 2024

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,410 320 Updated Nov 21, 2025

zynqmp-zcu102 hacks

19 5 Updated Sep 15, 2017

Style transfer, deep learning, feature transform

Python 11,189 1,197 Updated Jun 7, 2023

http://torch.ch

C 9,089 2,362 Updated Mar 31, 2025