MLIR For Beginners tutorial

A retargetable MLIR-based machine learning compiler and runtime toolkit.

Math library

Open Neural Network Exchange to C compiler.

Artifact Evaluation Reproduction for "Software Prefetching for Indirect Memory Accesses", CGO 2017, using CK.

A TAGE predictor for cbp4. Lab2 for Computer architecture, Tsinghua University.

vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器

Multi-objective Ensemble Design Space Exploration for CPU

A RISCV Emulator written in Python

The release codes of LA-MCTS with its application to Neural Architecture Search.

D-VAE: A Variational Autoencoder for Directed Acyclic Graphs, NeurIPS 2019

Memory latency test

A collection of benchmarks and tests for the Patmos processor and compiler

PolyBench/C benchmark suite (version 4.2.1 beta) from http://web.cse.ohio-state.edu/~pouchet/software/polybench/

RSD: RISC-V Out-of-Order Superscalar Processor

Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore designs

mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)

Release of stream-specialization software/hardware stack.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Swin Transformer C++ Implementation

Heterogeneous simulator for DECADES Project

Benchmarks for Accelerator Design and Customized Architectures

An unofficial mirror of the core PARSEC 3.0 benchmark suite with patches to run on x86_64 Arch Linux and generalize builds.