Lectures on the test generators course

llvm-snippy instruction sequence generator

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Wet Shader High Emotional Educational Expression Translator (ParaSL compiler)

Masters course revisited

Spike, a RISC-V ISA Simulator

Performance evaluation of some block ciphers

Virtual machine based on short ISA (ShISA)