Saleae plugin that analyzes basic SDIO protocol

This is a simple SDIO protocol analyzer plugin for Saleae Logic.

The code here is based on the Saleae example custom analyzer and borrows heavily from ewfuentes analyzer for settings and structure, but is a complete rewrite of the core analysis machine.

The Product// directories contained built plugin libraries. If you find one there that matches your OS, you can skip to "Using"

You can use the Xcode project here or the "build_analyzer.py" script. Both are tested on MacOS Catalina. Linux might work with the script.

Note that the build depends on you having the Saleae supplied AnalyzerSDK installed at the same directoy level as this code. This is a bit different than how Saleae lays out their sample.

Install the plugin by pointing Logic to the Analyzer path using "Preferences" menu. Saleae has documentation on how to do that. Restart Logic.

If you get a "can't dlopen" error on Mac, you need to go to the dir your dylib is in (depends on Xcode or cmdline, etc.) and

install_name_tool -change @executable_path/libAnalyzer.dylib @rpath/libAnalyzer.dylib libSDIOAnalyzer.dylib

Then restart Logic

SDIO should appear as an Analyzer choice. Click it, setup your channels and go.

Test on Linux/Windows

The Simulation data generation doesn't work quite right because there is only one channel asked for by Logic and SD needs at least cmd and clk, so the results are a bit garbage

There is no support for HS mode (data on rising clock or both clock edges)