Researcher, Computer Scientist.
Projects on EDA tools, digital hardware design, processor architectures, and software for embedded systems.
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Synopsys
- San Francisco Bay Area
- https://aletempiac.github.io/
- https://orcid.org/0000-0003-1312-2907
- @AleTempia
- in/alessandro-tempia-calvino
Stars
aletempiac / mockturtle
Forked from lsils/mockturtleC++ logic network library
C++ parsing library for simple formats used in logic synthesis and formal verification
ABC: System for Sequential Logic Synthesis and Formal Verification
Showcase examples for EPFL logic synthesis libraries