Location has moved to https://github.com/mermaid-js/mermaid-live-editor

Spark-TTS Inference Code

Generation of diagrams like flowcharts or sequence diagrams from text in a similar manner as markdown

Spatio-Temporal Based Concept Theory

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

AXI Adapter(s) for RISC-V Atomic Operations

Building Convolutional Neural Networks From Scratch using NumPy

Numpy implementation of deep learning

Neural Network Libraries

搭建、深度学习、前向传播、反向传播、梯度下降和模型参数更新、classification、forward-propagation、backward-propagation、gradient descent、python、text classification

Neural networks in NumPy/Cython

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Implements Binary Search Trees, AVL Trees, Splay Trees, and Red Black Trees in Python with plotting.

FuseSoC-based SoC for VeeR EH1 and EL2

The ultimate Vim configuration (vimrc)

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Async task manager with Celery-like features. Fork of arq.

豆瓣读书的爬虫

Integration layer between Requests and Selenium for automation of web actions.

Verilog Generator of Neural Net Digit Detector for FPGA

PySlowFast: video understanding codebase from FAIR for reproducing state-of-the-art video models.

Multi Task Vision and Language

Source code for Neural Information Processing Systems (NeurIPS) 2018 paper "Multi-Task Learning as Multi-Objective Optimization"

YOLO V2 & V3 , YOLO Combined with RCNN and MaskRCNN

CNN acceleration on virtex-7 FPGA with verilog HDL

Source Code of our CVPR2021 paper "Rethinking BiSeNet For Real-time Semantic Segmentation"

Verilog Code of a 5 stage pipelined, 32 bit RISC V processor - M extension with some DSP instructions also.