Stars
integration for Rynkowa cena energii elektrycznej (RCE)
FPGA board-level debugging and reverse-engineering tool
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
User space PTP stack for the GNU/Linux operating system.
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
A huge VHDL library for FPGA and digital ASIC development
Use any linux distribution inside your terminal. Enable both backward and forward compatibility with software and freedom to use whatever distribution you’re more comfortable with. Mirror available…
A data acquisition framework in Python and Verilog.
Riviera-PRO supports system simulation of Versal ACAP designs. These examples provide step-by-step instructions on how to use Riviera-PRO as the main RTL simulator for system simulation.
Control and status register code generator toolchain
List of awesome open source hardware projects
A usable language reference for VHDL that is concise, direct, and easy to understand.
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).
Open source FPGA-based NIC and platform for in-network compute
A translation of the Xilinx XPM library to VHDL for simulation purposes
A tiny Open POWER ISA softcore written in VHDL 2008
The lean application framework for Python. Build sophisticated user interfaces with a simple Python API. Run your apps in the terminal and a web browser.