Multi-level, sampled simulation using spike/uArch models/RTL for low latency, high fidelity, high throughput simulations

CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM stan…

DRAMSys a SystemC TLM-2.0 based DRAM simulator.

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

The Elixir Cross Referencer

mold: A Modern Linker 🦠

The system call intercepting library

A small library to modify all page-table levels of all processes from user space for x86_64 and ARMv8.

Watches files and records, or triggers actions, when they change.

libipt - an Intel(R) Processor Trace decoder library

Code for the USENIX 2017 paper: kAFL: Hardware-Assisted Feedback Fuzzing for OS Kernels

A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

Intermediate Language (IL) for Hardware Accelerator Generators

This repository contains booksim with modifications for Coyote

BookSim 2.0

Coyote is a simulator combining Spike and Sparta

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

Open-source high-performance RISC-V processor

Comparing the free tier offers of the major cloud providers like AWS, Azure, GCP, Oracle etc.

Modeling Architectural Platform

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

Doug Lea's malloc

A massively parallel, high-level programming language

A massively parallel, optimal functional runtime in Rust

A modern proof language

an educational compiler intermediate representation