Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Control and status register code generator toolchain

OBI SystemVerilog synthesizable interconnect IPs for on-chip communication

A reliable, real-time subsystem for the Carfield SoC

An interleaved high-throughput low-contention L2 scratchpad memory.

A dependency management tool for hardware projects.

DNN Compiler for Heterogeneous SoCs

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Wrapped, but for Weekly Reports

A Fast, Low-Overhead On-chip Network

SystemVerilog IPs and Modules for architectural redundancy designs.

Fight Manager Web Application for the SYPT

Fight Plan Generator for SYPT