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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Various HDL (Verilog) IP Cores

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Verilog library for ASIC and FPGA designers

GNU toolchain for RISC-V, including GCC

PicoRV32 - A Size-Optimized RISC-V CPU

Package manager and build abstraction tool for FPGA/ASIC development

A Video display simulator

Python script which can generate Reg map xml, excel, verilog

Verilog Generator of Neural Net Digit Detector for FPGA

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Controller for i2c EEPROM chip in Verilog for Mojo FPGA board

TangNano-9K-example project

FuseSoC-based SoC for VeeR EH1 and EL2

Verilog PCI express components

A work-in-progress for what is to be a software-free web server for static content.

A Verilog implementation of DisplayPort protocol for FPGAs

An open source SPI flash emulator and monitor

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

[Does not work anymore!] Script to enable systemd support on current Ubuntu WSL2 images

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An elegant \LaTeX\ résumé template. 大陆镜像 https://gods.coding.net/p/resume/git

The CNN based on the Xilinx Vivado HLS

SystemVerilog to Verilog conversion

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

A low power platform based on X-HEEP and integrating the ESL-CGRA

Pong game on an FPGA in Verilog.