OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Python-based Hardware Design Processing Toolkit for Verilog HDL

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Testbenches for HDL projects

Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores

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cocotb: Python-based chip (RTL) verification

Yosys Open SYnthesis Suite

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

VS Code in the browser

Visual Studio Code

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

RISC-V Formal Verification Framework

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSI…

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Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

A modern hardware definition language and toolchain based on Python

ASIC implementation flow infrastructure

An abstraction library for interfacing EDA tools

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

VeeR EH1 core

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

SystemVerilog synthesis tool

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …

SystemVerilog frontend for Yosys

SystemVerilog to Verilog conversion

Modular hardware build system