Currently learning:
Serial communication protocols in C and some C++ to the side
Popular repositories Loading
- 
      GT_VerilogGT_Verilog PublicLearning more about Verilog, Formal Verification, and Verilator - I am using Vivado with a Basys 3 board Tcl 1 
- 
      
- 
      ice40_ultraplus_examplesice40_ultraplus_examples PublicForked from damdoy/ice40_ultraplus_examples Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation Verilog 
- 
      
- 
      
- 
      
          Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
  If the problem persists, check the GitHub status page or contact support.