Skip to content
View aswaterman's full-sized avatar

Organizations

@ucb-bar @riscv @sifive @freechipsproject @chipsalliance

Block or report aswaterman

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Original RISC-V 1.0 implementation. Not supported.

Verilog 42 14 Updated Oct 4, 2018

Play your favorite games in a borderless window; no more time consuming alt-tabs.

C# 6,128 575 Updated Sep 5, 2025

mold: A Modern Linker 🦠

C++ 15,850 520 Updated Nov 11, 2025

Spike, a RISC-V ISA Simulator

C 2,903 997 Updated Nov 12, 2025

RISC-V Instruction Set Manual

TeX 4,353 771 Updated Nov 11, 2025

Chisel: A Modern Hardware Design Language

Scala 4,466 640 Updated Nov 11, 2025

Flexible Intermediate Representation for RTL

Scala 748 179 Updated Aug 20, 2024

Source files for SiFive's Freedom platforms

Scala 1,129 286 Updated Jul 17, 2021

Rocket Chip Generator

Scala 3,604 1,196 Updated Sep 2, 2025