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riscv Public
Forked from openhwgroup/cv32e40pRISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
SystemVerilog Other UpdatedMay 16, 2023 -
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pulpissimo Public
Forked from pulp-platform/pulpissimoThis is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
SystemVerilog Other UpdatedMar 20, 2019
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