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Shredos Disk Eraser 64 bit for all Intel 64 bit processors as well as processors from AMD and other vendors which make compatible 64 bit chips. ShredOS - Secure disk erasure/wipe

Makefile 2,634 115 Updated Oct 23, 2025

pySim SIM/USIM card reader/writer software

Python 27 1 Updated Dec 14, 2023

An rtl-sdr receiver for Itron ERT compatible smart meters operating in the 900MHz ISM band.

Go 2,384 262 Updated Feb 28, 2025

Program to decode radio transmissions from devices on the ISM bands (and other frequencies)

C 7,001 1,452 Updated Oct 29, 2025

Build, Store, and Distribute your Applications and Containers

Python 2,704 336 Updated Nov 12, 2025

Invidious is an alternative front-end to YouTube

Crystal 18,142 2,038 Updated Nov 10, 2025

Multi-platform nightly builds of open source digital design and verification tools

Shell 1,230 106 Updated Nov 12, 2025

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Verilog 80 12 Updated Oct 11, 2019

📐 Jekyll theme for building a personal site, blog, project documentation, or portfolio.

HTML 13,257 27,187 Updated Aug 31, 2025

Micro SD Card Adapter for Gamecube's Serial Port 2

129 23 Updated Nov 6, 2019

OpenHantek is a DSO software for Hantek (Voltcraft/Darkwire/Protek/Acetech) USB digital signal oscilloscopes

C++ 800 203 Updated Apr 11, 2024

Pycord is a modern, easy to use, feature-rich, and async ready API wrapper for Discord written in Python

Python 2,899 478 Updated Nov 12, 2025

Cross-Platform SDR Software

C++ 5,284 729 Updated Oct 9, 2025

C++ library for creating an embedded Rest HTTP server (and more)

C++ 938 192 Updated Aug 24, 2025

There are many RISC V projects on iCE40. This one is mine.

AGS Script 14 4 Updated Jun 25, 2020

RISC-V Formal Verification Framework

Verilog 615 103 Updated Apr 6, 2022

RISC-V instruction set simulator built for education

Kotlin 218 64 Updated Apr 2, 2022

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 1,903 293 Updated Nov 7, 2025

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala 2,030 781 Updated Oct 30, 2025

A Linux-capable RISC-V multicore for and by the world

SystemVerilog 745 194 Updated Nov 8, 2025

EmotiVoice 😊: a Multi-Voice and Prompt-Controlled TTS Engine

Python 8,370 735 Updated Aug 13, 2024

The OpenLog Artemis is an open source datalogger the comes preprogrammed to automatically log IMU, GPS, serial data, and various pressure, humidity, and distance sensors. All without writing a sing…

C++ 98 50 Updated Nov 8, 2025

Learning FPGA, yosys, nextpnr, and RISC-V

C++ 3,258 307 Updated Feb 25, 2025

Firmware and software support for the pico-ice board

C 67 21 Updated Oct 5, 2025

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Python 1,103 234 Updated Sep 22, 2025

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

C 4,410 737 Updated Nov 8, 2025

A tiny C header-only risc-v emulator.

C 2,002 150 Updated May 4, 2025

An unofficial assembly reference for RISC-V.

TeX 512 63 Updated Nov 12, 2024

GNU toolchain for RISC-V, including GCC

C 4,229 1,311 Updated Nov 4, 2025
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